Improved Circuit-to-CNF Transformation for SAT-based ATPG
نویسندگان
چکیده
SAT-based ATPG has proven to be a beneficial complement to traditional ATPG techniques. The generation of a CNF-representation is a vital issue in SAT-based test pattern generation. Firstly, the generation of the problem instances for SAT-based ATPG requires a significant portion of the overall runtime. Secondly, the performance of the SAT solver strongly depends on the properties of the resulting CNF-representation. The contribution of this paper is a new approach to generate CNF-representations for SAT-based ATPG. The objective of the proposed technique is to speed up the generation process and to optimize the resulting CNF-representation with respect to the SAT computation. The experimental results, obtained on large industrial designs, show that the accomplished optimizations result in a significant reduction of the overall runtime of the SAT-based test pattern generation process. Finally we discuss how this contribution enables some promising future work.
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